Models of computation for NoC mapping: Timing and energy saving awareness

César Marcon*, Thais Webber, Altamiro Amadeu Susin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


A complex application implemented as a System-on-Chip (SoC) demands extensive system level modeling. Its implementation encompasses a large number of cores and an advanced interconnection scheme such as a Network-on-Chip (NoC). This type of application normally requires energy efficiency and execution time minimization, which implies high-level exploration for cores/tasks placement into the target architecture. A Model of Computation (MoC) captures some characteristics of the applications aiming to fulfill high-level explorations. This work analyzes MoCs employed on the static and dynamic mapping of applications onto regular NoCs, providing a classification based on aspects of computation and communication. Additionally, this paper discusses advantages and drawbacks of these MoCs, such as the complexity of capturing application aspects, as well as the mapping quality. Finally, this work implements the five MoCs more applied on the mapping and compares them applying a benchmark composed of synthetic and embedded applications running on various NoC sizes.

Original languageEnglish
Pages (from-to)129-143
Number of pages15
JournalMicroelectronics Journal
Early online date4 Jan 2017
Publication statusPublished - 1 Feb 2017

Bibliographical note

Publisher Copyright:
© 2016 Elsevier Ltd


  • Application modeling
  • Energy minimization
  • Mapping
  • Network-on-Chip (NoC)
  • Performance analysis


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